The present invention pertains to controllers for operating a telecommunication process and more particularly to internal clock synchronization of multiple central processing units.
Public policy requires that telecommunication systems provide virtually uninterrupted service to its subscribers over long periods of time. Providing redundant circuitry is an aid in meeting this public policy requirement.
However, simple duplication of circuitry creates a problem of simultaneous operation of the circuitry. In order to meet the objective of no loss of service for long periods of time, it is undesirable for telecommunication system outages to occur during a change-over from one copy of the duplicated circuitry to the redundant back-up copy of the circuitry.
Modern telecommunication systems employ multiprocessing arrangements of central processing units in order to accomplish their switching operations. The central processing units (CPUs) of this multiprocessing arrangement may be synchronized in order to avoid loss of service during change-over operations. Typically, central processing unit synchronization has been performed by a vast amount of clock circuitry, which provides the driving signals to the CPUs. With the advent of single chip microprocessor CPUs, this synchronization function is made difficult. Since much of the clocking function of these single chip microprocessor CPUs is internal to the chip package, synchronizing multiple CPU is more complex.